A programmable logic device (PLD) is a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost. An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) from an external source into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. Thus, the collective states of the individual configuration memory cells determine the function of the FPGA.
A well-studied occurrence in circuitry is called Single Event Upset (SEU). SEU is an inadvertent change in state of a circuit caused by an external energy source such as, for example, cosmic rays, alpha particles, energetic neutrons, and the like. The energetic particles may randomly strike a semiconductor device and penetrate into the substrate (e.g., transistor source and drain regions) of the semiconductor device. These particle strikes create pairs of electrons and holes, which in turn cause undesirable transients that may upset circuit elements such as, for example, flipping the logic state of a latch or other memory element. As fabrication geometries and supply voltages continue to decrease, SEU problems become more severe. As a result, efforts to reduce SEU problems are increasingly important.
In a conventional DRAM or SRAM, SEU may be addressed with well-known error correction techniques. However, error correction may not be practical for FPGA configuration memory cells. For example, because an FPGA's configuration memory cells define how the FPGA's CLBs, IOBs, and interconnect structure are configured, inadvertent state changes in the configuration memory cells resulting from SEU transients may alter how the FPGA operates.
One approach to remedy SEU problems in configuration memory cells is to use triple modular redundancy (TMR). With TMR, individual memory cells are replaced with three sets of memory cells and configurable logic, where the outcome of at least two of the three sets controls FPGA operation. However, implementing TMR in an FPGA undesirably increases the size and cost of the FPGA.
Others have attempted to increase resiliency to SEU transients. For example, FIG. 1 shows an SEU-resistant memory cell 100 of the prior art. Memory cell 100 is a latch having cross-coupled inverters 102 and 104 coupled between complementary data terminals D and D. Resistor R1, which is coupled between inverter 102 and inverter 104, delays transients caused by SEU particle strikes at the output of inverter 102 from reaching the input (and possibly changing the state) of inverter 104, which in turn gives inverter 104 more time to reset inverter 102 to its correct state. Similarly, resistor R2, which is coupled between inverter 104 and inverter 102, delays transients caused by SEU particle strikes at the output of inverter 104 from reaching the input (and possibly changing the state) of inverter 102, which in turn gives inverter 102 more time to reset inverter 104 to its correct state.
To provide SEU resiliency, resistors R1 and R2 each have a resistance of between approximately 100 kilo-ohms and one mega-ohm. Unfortunately, the formation of such large resistors consumes a relatively large amount of area and complicates integration with complementary-metal-oxide semiconductor (CMOS) processes.
Accordingly, it would be desirable and useful to provide an SEU-resistant memory circuit that consumes minimal silicon area and is suitable for integration with a CMOS process.